1. Field of Invention
This invention relates to a semiconductor device, and more particularly relates to an electrostatic discharge (ESD) device and a semiconductor structure derived from it.
2. Description of Related Art
For sufficient ESD robustness of the ESD devices in CMOS integrated circuits, a salicide (self-aligned silicide) blocking (SAB) layer can be disposed on the drain-side diffusion to block salicide formation thereon and thus prevent current localization and provide a ballast resistance to increase the current uniformity at the drain-side.
FIG. 1 illustrates a layout of a series of conventional ESD devices with shared source/drain regions. Each ESD device includes a gate line 110 on a substrate 100, a source region 120 at one side of the gate line 110, a drain region 130 at the other side of 110 shared with another ESD device, a ring-shaped SAB layer 140 partially covering the drain region 130, a salicide layer 150 on the source region 120 and on the portions of the drain region 130 not covered by the SAB layer 140, contact plugs 160a on the salicide layer 150 on the source region 120, and contact plugs 160b on the salicide layer 150 on the drain region 130 surrounded by the SAB layer 140.
However, in an advanced process forming high-k gate dielectric and metal gates, a SAB layer may not be present. Hence, a design that sustains high ESD robustness in fully salicided ESD devices is required. Though increasing the distance (Dcg) between the gate line 110 and the nearest contact plugs 160b in the conventional ESD devices can prevent current localization and provide a larger ballast resistance to enhance the ESD robustness, the area of drain-side diffusion or the ESD device is much increased.